Generative engineering · Case study
AI-Assisted PCB Design
A public engineering prototype that transforms natural-language ESP32 sensor-board requirements into a structured, reviewable handoff with component choices, BOM, pin maps, netlists, power budgets, readiness checks, and layout guidance.
Generative engineeringProject overview
AI-Assisted PCB Design
A public engineering prototype that transforms natural-language ESP32 sensor-board requirements into a structured, reviewable handoff with component choices, BOM, pin maps, netlists, power budgets, readiness checks, and layout guidance.
- Release
- Version 5.1.0
- Role
- System designer and developer
- Modes
- Base, Ollama/Qwen2.5, and Gemini
- Output
- Reviewable ESP32 engineering handoff
- Status
- Live public prototype
The problem
Useful hardware guidance must be complete, consistent, and reviewable
Language models can produce plausible hardware recommendations while omitting constraints or introducing inconsistencies across components, pins, power, and connectivity. Engineers need structured artifacts and explicit checks, not an untraceable block of generated advice.
The system
Generation followed by deterministic engineering checks
The workflow separates controlled interpretation, structured generation, deterministic validation, and presentation. Base mode works without an external model; Ollama and Gemini outputs are validated and fall back safely when unavailable or invalid.
What I built
A safer path from prompt to engineering artifact
Designed a guided requirements workflow for supported ESP32 boards, sensors, interfaces, and operating constraints.
Produced structured component selections, bill-of-material details, pin assignments, netlists, and power-budget information.
Added deterministic validation and fallback behavior so the workflow does not depend on a model response alone.
Included unsupported-request handling and review cues that make scope and uncertainty visible to the user.
Built a Streamlit interface that keeps inputs, validation status, and generated engineering artifacts easy to inspect.
Added a source-grounded PCB Review Copilot with Gemini-first answers and deterministic local review when Gemini is unavailable.
Quality and evaluation
Validation is part of the product, not a final decoration
Checks cover structured output, supported hardware scope, pin and component consistency, design-readiness status, and deterministic fallback paths.
This is a review prototype, not an autorouter or fabrication tool. It does not generate KiCad projects or Gerber files and does not replace electrical simulation, certification, or professional engineering review.
Technology
Evidence